MSTCONTINUE=NO_EFFECT, MSTDMA=DISABLE, MSTSTOP=NO_EFFECT, MSTSTART=NO_EFFECT
Master control register.
| MSTCONTINUE | Master Continue. This bit is write-only. 0 (NO_EFFECT): No effect. 1 (CONTINUE): Continue. Informs the Master function to continue to the next operation. This must done after writing transmit data, reading received data, or any other housekeeping related to the next bus operation. |
| MSTSTART | Master Start control. This bit is write-only. 0 (NO_EFFECT): No effect. 1 (START): Start. A Start will be generated on the I2C bus at the next allowed time. |
| MSTSTOP | Master Stop control. This bit is write-only. 0 (NO_EFFECT): No effect. 1 (STOP): Stop. A Stop will be generated on the I2C bus at the next allowed time, preceded by a NACK to the slave if the master is receiving data from the slave (Master Receiver mode). |
| MSTDMA | Master DMA enable. Data operations of the I2C can be performed with DMA. Protocol type operations such as Start, address, Stop, and address match must always be done with software, typically via an interrupt. When a DMA data transfer is complete, MSTDMA must be cleared prior to beginning the next operation, typically a Start or Stop.This bit is read/write. 0 (DISABLE): Disable. No DMA requests are generated for master operation. 1 (ENABLE): Enable. A DMA request is generated for I2C master data operations. When this I2C master is generating Acknowledge bits in Master Receiver mode, the acknowledge is generated automatically. |
| RESERVED | Reserved. Read value is undefined, only zero should be written. |